One of methods for achieving a low power operation in a microprocessor is an instruction discriminating method (e.g., Japanese Patent No. 2778583).
FIG. 1A is a structural diagram showing a low power operation control unit according to conventional instruction discrimination. FIG. 1B is an operational flow showing the low power operation control unit according to the conventional instruction discrimination.
In FIG. 1, an inputted instruction is decoded by a decoder (101), low power control contents are decided by a low power control circuit (102) based on a decoding result, and control is performed by a control signal (103), which stops the clock of a specific block, according to a decision result.
Further, another one of methods for achieving low power operation is a low power instruction set discriminating method (e.g., Japanese Patent Laid-Open No. 2001-184208).
FIG. 2A is a structural diagram showing an instruction set used for a conventional microprocessor. FIG. 2B is a structural diagram showing a low power operation control unit according to the conventional discrimination of an instruction set. FIG. 3 is an operational flow showing the low power operation control unit according to the conventional discrimination of an instruction set.
In FIGS. 2 and 3, in a low power instruction set which can be switched with a normal instruction set, the number of instructions is limited to generate a space in an instruction code format, and a format is set to define the contents of low power control in the space of the instruction code. The normal instruction set and the low power instruction set each has an instruction decoder (201). When the low power instruction set is used, low power control contents are decided by a low power control circuit (202), and control is performed by a control signal (203), which stops the clock of a specific block, according to a decision result.
However, regarding the above methods, in the instruction discriminating method of FIG. 1B, it is difficult or impossible to control a pipeline stage of an instruction decode and a preceding pipeline stage on a principle of decoding an instruction and performing control.
Moreover, in the low power instruction set discriminating method, information for low power control is acquired from a place other than an instruction decode and thus it is possible to control the pipeline stage of the instruction decode and a preceding pipeline stage. However, it is necessary to provide a plurality of instruction decoders and a circuit for selecting an instruction decode result according to a used instruction set and thus signal transmission paths (204) are increased by a larger circuit size, thereby increasing power consumption and decoding time.
In view of the above problem, an object of the present invention is to control the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time, and achieve a low power operation of a microprocessor.